The present invention relates to flash memory systems, and more specifically, to an architecture for a state machine used to control the internal data processing operations of a flash memory. The state machine uses a central controller to control the execution of the sub-operations common to the data processing operations. The state machine of the present invention has fewer logic gates and is more compact than the set of state machines currently used for such purposes.
In early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. Since the operation of many memory systems requires a substantial amount of processor overhead, many such systems now include an internal state machine for controlling the detailed operation of the memory system. The internal state machine controls the primary operations of the memory system, including the reading, programming and erasing operations performed on the memory elements. Each of these primary operations is comprised of a large number of sub-operations which are necessary to carry out the primary operations, with these sub-operations also being controlled by the primary state machine or in some cases by a secondary one.
FIG. 1 is a functional block diagram of a conventional flash memory system 100. The core of memory system 100 is an array 112 of flash memory cells. The individual cells in array 112 are arranged in rows and columns, with there being, for example, a total of 256 K eight bit words in array 112. The individual memory cells (not shown) are accessed by using an eighteen bit address A0-A17, which is input by means of address pins 113. Nine of the eighteen address bits are used by X decoder 114 to select the row of array 112 in which a desired memory cell is located and the remaining nine bits are used by Y decoder 116 to select the appropriate column of array 112 in which the desired cell is located. Sense amplifiers 119 are used to read the data contained in a memory cell during a read operation or a data verification step in which the state of a cell is determined after a programming, pre-programming, or erase operation. This circuitry can be combined with the data compare and verify circuits used to compare the state of a cell to a desired state or to input data.
Memory system 100 contains an internal state machine (ISM) 120 which controls the data processing operations and sub-operations performed on memory array 112. These include the steps necessary for carrying out programming, reading and erasing operations on the memory cells of array 112. In addition, internal state machine 120 controls such operations as reading or clearing status register 126, identifying memory system 100 in response to an identification command, and suspending an erase operation. State machine 120 functions to reduce the overhead required of an external processor (not depicted) typically used in association with memory system 100.
For example, if memory cell array 112 is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin {overscore (OE)} to be inactive (high), and the chip enable {overscore (CE)} and write enable {overscore (WE)} pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins 115 (DQ0-DQ7), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command DOH (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation so as to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins 115 are transferred to data input buffer 122 and then to command execution logic unit 124. Command execution logic unit 124 receives and interprets the commands which instruct state machine 120 to initiate the steps required for erasing array 112 or carrying out another desired operation. Once the desired operation sequence is completed, state machine 120 updates 8 bit status register 126. The contents of status register 126 is transferred to data output buffer 128, which makes the contents available on data I/O pins 115 of memory system 100. Status register 126 permits the external processor to monitor certain aspects of the status of state machine 120 during memory array write and erase operations. The external processor periodically polls data I/O pins 115 to read the contents of status register 126 in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
FIG. 2 is a state diagram showing the states of an erase state machine during the performance of an erase operation on a memory system such as that shown in FIG. 1. As indicated by the figure, an erase operation includes pre-program 200, high voltage (internal) erase 220, and erase healing (distribution adjustment) 240 stages. As shown in the figure, each of these primary stages in an erase operation is typically implemented in the form of a separate state machine.
The erase operation begins with an erase set-up stage 260 which is initiated by application of the appropriate commands on data I/O pins 115 (DQ0-DQ7) of FIG. 1, and any other appropriate control signals applied on the relevant lines. The function of stage 260 is to set up a node that indicates that the part is being erased. From this state, the state machine either transitions to pre-program state 200 along path 262, or if instructed to skip that stage, along path 264. If the state machine transitions to the pre-program stage, pre-program state machine 200 then carries out that operation. This sub-operation programs all the elements in the memory array to a logic 0 value to make sure that the erase process starts from a known cell threshold voltage level. This part of the complete erase operation is used to reduce the possibility of over erasure of some of the memory elements during the later steps. When the pre-program operation has been completed on the memory elements, the erase state machine transitions along path 265 to the next stage, unless the state machine has been instructed to suspend the erase operation. If a problem occurs during the pre-program stage, control is passed out of that stage along path 263.
When the pre-program operation is complete, or if that operation was skipped, the erase state machine transitions to erase high voltage (internal erase) stage 220. As noted in FIG. 2, this stage is typically implemented in the form of a state machine. In the erase high voltage stage, the memory system performs a block erase operation on all of the cells contained in a block of memory. This has the effect of erasing all of the memory elements to a logic 1 value.
Upon successful completion of the high voltage erase operation, the erase state machine transitions to either the erase healing stage 240 or to the erase clean up stage 270. If the erase operation was successful and the heal operation has not been performed, the erase state machine transitions along path 266 to healing state machine 240. In the erase healing operation, the memory cells in the array are corrected (if necessary) for the effects of accidental over-erasure, in which case the threshold voltage of a cell has been driven down to zero or a negative value. When this operation has been completed for the block of memory elements which has been erased, the erase state machine transitions back along path 268 to the erase high voltage state machine 220. This is because the erase high voltage operation may need to be repeated to further adjust the threshold voltage levels of the memory cells after they have been altered by the healing operation. This cycle can be repeated until the erase high voltage operation and the healing operation have produced a desired range of threshold voltage levels. At that point, the erase state machine transitions along path 267 to erase clean up state 270. This stage is used to condition all internal nodes of the memory array to default values in order to prepare the memory system for the next operation. In addition, if an erase high voltage state error occurs, the state machine transitions along path 269 to erase clean up state 270.
FIG. 3 is a state diagram showing the states of the erase state machine of FIG. 2 in greater detail, and in particular the states of the pre-program, erase high voltage, and healing state machines shown in that figure. The pre-program cycle begins with pre-program state machine 200 initiating an operation which increments the address of the memory cell which is to be pre-programmed 202. This is done because the pre-programming operation is executed on a cell by cell basis. This step is followed by a high voltage level set-up stage 204 which prepares the system for application of the high voltage levels (typically, about 12 volts is applied to the gate of each memory cell and 6 volts to the drain) used for programming or erasing a cell. The high voltage level used for writing to (programming) the cell is then applied in stage 206.
The appropriate voltage levels for executing the data verification sequence (reading the data pre-programmed in the cell and comparing it to a desired value) are checked for at stage 208. This is followed by a program verification stage 210 which verifies that the programmed cell has sufficient margin. This is typically accomplished by reading the data stored in a cell and comparing it to a logic 0 value. If the verification operation was not successful, steps 204, 206, 208, and 210 are repeated. Once the verification stage for a particular memory cell is successfully completed, it is followed by a program clean up stage 212. Program clean up stage 212 conditions all internal nodes of the memory array to default values in order to prepare the memory system for the next operation. This concludes the pre-programming cycle for a given memory cell. The address of the cell to be operated on is then incremented at stage 202 and the process repeats itself until the last cell in a memory block to be erased is programmed. At this time, the incremented address will be set to the first address location in the block, which is the first address for the next operation. When this occurs, all of the memory cells have been successfully pre-programmed and control is passed to the erase high voltage state machine 220.
In the high voltage erase cycle, the memory system performs a block erase operation on all of the cells contained in a block of memory. The first stage in the cycle is a high voltage level set-up stage 222 which prepares the memory block for application of the high voltage pulse(es) used for erasing the cells. This is followed by a high voltage stage 224 in which a high voltage pulse is applied to erase all of the memory cells in the block of cells. This is followed by a set-up verify stage 226 which checks to see that the appropriate voltage levels for the data verification stage are present. The next stage is an erase verify stage 228 which verifies that the erase operation was successfully carried out on each cell in the block. This is accomplished by stepping through the cells, address by address and reading the data in a cell and comparing it to a logic value of 1.
If the erase operation was not successfully carried out (a cell was not erased to the proper threshold voltage margin to have the desired logic value), control is passed back to the high voltage level set-up stage 222 and the high voltage cycle is carried out again to erase the entire block of cells. If the erase operation was successful for the cell under consideration, the address of the memory cell is incremented 230 and the next cell is tested for verification of the erase operation. Thus, if the maximum address of the cells in the block of memory has not been reached, the erase verify stage is carried out on the next memory cell in the block. If the maximum address for cells in the block has been reached (meaning that all cells in the memory block have been successfully erased), control is passed to the distribution adjustment or healing state machine 240.
The distribution adjustment sub-operation 240 is used to tighten the distribution (reduce the variance) of the threshold voltages of the erased memory elements. The distribution adjustment or healing operation is implemented by applying high voltages (i.e., 12 volts) to the gates of all the memory cells in the memory block, with the memory cell drains floating and the sources at ground potential. This is designed to compensate for the effects of over erasure of any of the memory cells and to tighten the distribution of threshold voltages of the cells. The distribution adjustment cycle begins with a high voltage set-up stage 242, which is followed by a high voltage stage 244 in which the voltages used to perform the healing operation are applied. This is followed by a set-up verification 246 stage which checks to see that the appropriate voltage levels for the data verification operation are present, and erase verification 248 stage which acts to insure that all of the erased cells are still in an erased state. If the erase verification procedure fails, a final erase 249 stage may be executed. In the final erase stage, a short erase pulse is applied to the cells in the block.
After completion of the healing cycle, control is passed back to the erase high voltage state machine 220 along path 268 of FIG. 2. The erase state machine then transitions to erase clean up state 270 of FIG. 2. Erase clean up stage 270 conditions all internal nodes of the memory array to default values in order to prepare the memory system for the next operation. At this point the erase operation is completed.
FIG. 4 is a state diagram showing the states of a program state machine during the performance of a programming operation on a memory system such as that shown in FIG. 1. It is noted that a programming operation can be carried out by following the states shown in the pre-program cycle of the complete erase operation of FIG. 3. In particular, stages 204 through 212 of FIG. 3 describe the primary functions carried out in a regular programming operation. As a program operation is typically carried out on a specific memory cell, the increment address state 202 used in the pre-program cycle to facilitate pre-programming of every cell in the memory array is not accessed.
Another difference between the programming and pre-programming operations is that in a programming operation, program verify state 210 is designed to read the programmed data and compare it to the input data, rather than to a logic value of 0, as in the pre-programming operation. Increment counter state 211 of FIG. 4 is used to increment the pulse counter in the event that the programming operation failed. This allows the state machine to track the number of voltage pulses applied to a cell when the programming operation is re-tried on that cell. If the maximum pulse count value has not been reached, the state machine transitions back to program level setup state 204 and the programming operation is tried again on that cell. If the maximum pulse count value has been reached, the state machine transitions to program clean-up state 212.
It is noted that the distinct stages of the operation of the data processing operations performed on the memory cells shown in FIGS. 3 and 4 are typically implemented as separate circuits. Thus, the erase pulse control, program pulse control, and heal pulse control functions are usually executed by separate circuits, leading to the duplication of some of the functionality. The same situation occurs for erase verify stage 228 and program verify state 210, thus resulting in additional duplication of circuitry.
While the state machine architecture of FIGS. 2-4 can be used to control the programming and erase operations carried out on a memory cell, it does have significant disadvantages. Firstly, a separate state machine is typically used to perform each function, and as noted, in some cases sub-functions. Since each state machine is constructed from multiple logic gates, this means that an enormous number of gates are required to construct a complete state machine of this design. A direct implementation of the state machines shown in FIGS. 3 and 4 would require approximately 20-25 states, and with 20 logic gates per state, this would give a total of 400 to 500 gates for the entire state machine. As some of the operations carried out by different state machines are similar in function, this results in a duplication of some of the logic gates. For example, the stages of a pre-program operation largely duplicate those of a program operation, and the setup and application of voltage pulses stages, the setup verification and date verification stage are common at a functional level in both the programming and erase operations. This duplication of functions produces an inefficient, less compact, and more expensive design for the complete state machine.
A second disadvantage to the state machine architecture of FIGS. 2-4 is that it produces a basically linear or sequential process flow. By this is meant that each state machine contains a set of operations which are carried out in a prescribed order prior to passing control to the next state machine, with the state machines themselves being implemented in a prescribed order. This structure is related to the previously mentioned problem, as this process flow leads to the duplication of functions in the state machine and in the modules controlled by the state machine, such as timers and counters. A disadvantage of this organization is that it reduces the ability to vary the process flow in order to test a product or produce specialized parts.
What is desired is a state machine architecture for controlling the data processing operations performed on the memory cells of a memory array which is implemented in a more efficient and flexible manner than currently used architectures. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
The present invention is directed to an architecture for a state machine used to control the data processing operations performed on the memory cells contained in a memory array. The architecture is designed to control the performance of the operations and sub-operations used to erase and program the memory array. The architecture of the present invention does not utilize separate state machines for each primary operation, but instead is based on a single state machine which is capable of controlling the various functions common to the data processing operations carried out on the memory cells.
The state machine of the present invention includes a sequencer module which acts upon commands input from an external microprocessor and determines which set of sub-operations or functions need to be performed to implement the commanded operation. The sequencer activates a timer which acts to trigger the functions controlled by a loop controller as they are needed for a particular operation. The sequencer provides input signals to the loop controller which are used to determine the parameters of the signals generated by the loop controller. The signals output from the loop controller are used to control the high voltage supplies which produce the pulses for erasing or programming the cells. The loop controller also provides an input signal which causes a pulse counter to increment the pulse count and an address counter to increment the cell address as required during the execution of a program or erase operation.
By using the sequencer to control the order in which each of several common functions is performed, the architecture of the state machine can be simplified compared to presently used state machines. This results in a reduction in the size, number of logic gates, and complexity of the state machine. It also produces a state machine in which the order of each of the functions or sub-operations can be varied as desired, rather than being required to follow a prescribed order which cannot be altered.
Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.